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Digital-DCTM Frequently Asked Questions
What is the Digital-DC?
Digital-DC is an innovative mixed-signal power conversion and management architecture that combines a compact, efficient, synchronous buck controller, adaptive drivers and key power and thermal management functions in one IC. Digital-DC devices also incorporate an I2C/SMBus hardware interface with full PMBus compliance, including support for over 100 PMBus commands.
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What is PMBusTM?
PMBus is a power management protocol that allows users to easily configure and monitor all aspects of the DC-DC converter circuit through an I2C or SMBus™ hardware interface. Digital-DC devices support over 100 PMBus commands. For PMBus specifications and more information, please see the official PMBus web site at http://pmbus.org/.
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Are Digital-DC devices compatible with extended temperature environment?
Yes. Digital-DC devices are specified for an operating junction temperature of -40 to 125 °C. The absolute maximum junction temperature is 150 °C.
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What is the reference tolerance (and output accuracy) on Digital-DC devices?
The initial tolerance of the internal voltage reference is less than 0.4%. The output voltage accuracy is guaranteed to be ±1% over line, load, and temperature conditions. The total output accuracy is typically within 3% of the configured output voltage including output ripple and transient variations given adequate design of the output filter stage.
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What is the maximum output current?
The maximum output load varies for each device. ZL2105 with integrated MOSFETs can supply up to 3A. The ZL2005 is a DC-DC controller with integrated synchronous MOSFET drivers and is capable of producing output currents up to 40A by selecting the appropriate external power components (MOSFETs, inductor, and filter capacitors) and using good design practices. For output currents greater than 15A, additional attention to thermal design is recommended in order to assure the application circuit will operate reliably within the recommended thermal guidelines.
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Do Digital-DC devices offer soft-start capability?
Yes. Digital-DC devices can be configured to achieve its target voltage instantaneously (limited by capacitance present) or to ramp monotonically to its target voltage based on a pre-configured value between single-digit milliseconds and several seconds. A start-up delay, with an initial minimum time, can also be configured up to 200 ms.
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Do you offer pre-bias start-up capability?
Yes. All Digital-DC devices provide monotonic start-up into a pre-biased load. A feature unique to Digital-DC devices is their ability to maintain the same ramp-up timing regardless of the pre-bias voltage level.
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Do Digital-DC devices offer sequencing between multiple devices?
Yes. Using the start-up ramp procedure discussed above, multiple devices can be configured to start at any desired rate and/or sequence. Sequencing can be time based or event based and can be re-configured using PMBus commands without any hardware modifications.
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Do Digital-DC devices offer voltage margining?
Yes. The output on Digital-DC can be margined by toggling the MGN pin. The default limits are set to ±5% but can be modified as low as ±1% or as high as +10%/-100% using PMBus commands. The +10% margin limit is a hardware limit intended to protect sensitive circuitry from being subjected to an over-voltage condition.
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Do Digital-DC devices offer voltage tracking?
Yes. Any Digital-DC device can track any other supply by connecting the VTRK pin of the following device to the output that is to be tracked. Tracking can be coincidental (all voltages track each other during ramp-up and ramp-down only) or ratio-metric (one voltage tracks another at a specific %). The ratio-metric default is for the tracking device to follow at 50% of the voltage being tracked, as required for DDR memory applications. This ratio may be modified using a voltage divider.
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Can you reconfigure a part for tracking or to regulate at its own target without modifying hardware?
Yes, all Digital-DC parts can be modified using a simple PMBus command to vary between tracking another voltage at a specific percentage or regulating at its own target voltage. No hardware changes needed if the required tracking input voltage connection is incorporated into the board design. The ZL2105 has been designed for use as a VTT termination supply such that it can do 50% tracking (or 100% tracking) and sink/source current.
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Do Digital-DC devices offer system monitoring?
Yes. Digital-DC devices can monitor a wide variety of input and output parameters as well as power conversion parameters. A partial list of parameters that can be monitored include input voltage, output voltage, output current, internal temperature, external device temperature, switching frequency, duty cycle, MOSFET dead-times, and fan speed. Please contact the factory for a full list of parameters that can be monitored.
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Do Digital-DC devices support phase interleaving between devices?
Yes. Digital-DC devices can be configured to start its switching cycle at 22.5° increments. This allows multiple devices connected in parallel to draw their input current at different intervals, thus reducing the instantaneous current drawn from the input and allowing the use of fewer input capacitors.
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How do you set the device address when using multiple parts on the SMBus?
Digital-DC devices include either one or two pins for setting the SMBus address. By pin-strapping these pins the user can set unique bus addresses for multiple devices that are being used on the same physical bus.
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How can we determine the compensation coefficients A, B, C?
Zilker Labs provides a software tool, CompZL, to provide an automatic calculation of the 3 coefficients based on the power train selected and the target cross over frequency, gain and phase margin. The software will provide resulting bode plot and adjust automatically the PID coefficients for optimal performance. Please contact your sales office for a copy of the latest software revision.
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Can we change the PID taps on the fly without cycling power?
Yes, changing PID settings on the fly is allowed. The PMBus command to do this writes all three PID tap settings simultaneously. This is not however recommended to change the PID taps during operation
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What protection features are supported in Digital-DC devices?
Digital-DC devices support protection features including input under-voltage protection, output over-voltage and under-voltage protection, output over-current and under-current limiting, and device over-temperature limiting. Please contact the factory for other protection features.
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How is current limiting implemented on Digital-DC devices? What is the sensing accuracy?
Most Digital-DC devices incorporate both low-side MOSFET RDS(ON) sensing and inductor DCR sensing. The response time and method to a current fault event can be adjusted by the user. Current sensing accuracy depends on the method used; a precision sense resistor may be used in both modes for higher accuracy. Additionally, the device can use the internal or external temperature sensor to calibrate for the typical temperature coefficient of the sensing element used, enabling higher accuracy.
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What is the thermal capability of the QFN package?
Digital-DC devices are packaged in QFN packages. The 6mm x 6mm package specifies a ΘJ-PCB of approximately 12°C/W and a ΘJV (Junction to vias) of 6°C/W. These values will mainly depend on board layout, copper thickness. For more detailed information on the QFN package, please refer to Application Note AN10: ZL2005 and ZL2105 Thermal and Layout Guidelines.
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How is thermal limiting implemented on Digital-DC devices? Can the thermal shutdown limit be modified?
Digital-DC devices are pre-configured to shut down at an internal junction temperature of 125°C. Once the internal junction temperature reaches 125°C, the device will shut down and allow the device to cool. Once the junction temperature drops approximately 10°C below the pre-configured thermal limit, the device will attempt to turn on again. The thermal shutdown threshold and the number of retry attempts is configurable by the user. Setting the thermal limit above 130°C is prohibited to prevent thermal overstress to the device.
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Provide details on fault thresholds and the timing of monitoring activities.
The faults monitored are as follows:
- Input Overvoltage (IOV) is monitored by the Aux ADC on a 4ms sampling basis against a 10-bit programmable threshold.
- Input Undervoltage (IUV) is monitored by a hardware comparator against a 6-bit programmable threshold. Shutdown is accomplished within gate propagation delays after a programmable number of undervoltage violations.
- Output Overvoltage (OOV) is monitored by a hardware comparator against a 10-bit programmable threshold. Shutdown is accomplished within gate propagation delays after a programmable number of overvoltage violations.
- Output Undervoltage (OUV) is monitored by a hardware comparator against a 10-bit programmable threshold. Shutdown is accomplished within gate propagation delays after a programmable number of undervoltage violations.
- Overcurrent (OCP) is monitored by a mixed-signal implementation which checks the current limits on alternate switch cycles. The threshold is set as a positive or negative multiple of 3% of full-scale current.
- Undercurrent (UCP) (for negative current) is monitored by a mixed-signal implementation which checks the current limits on alternate switch cycles. The threshold is set as a positive or negative multiple of 3% of full-scale current.
- Overtemperature (OTP) is monitored by the Aux ADC on a 4ms sampling basis against a 10-bit programmable threshold. The measured temperature is then filtered which slows the response from the 4 ms loop time.
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How do you implement fault spreading between multiple Digital-DC devices?
Fault spreading is turned on when sequencing is turned on as described in the device data sheet. Fault spreading requires the devices to be connected through the SMBus. Fault spreading can also be turned on through the PMBus. SMBus_TX_Inhibit needs to be set to ‘Transmit Enabled’ so the device will transmit faults and Fault_Spread_Control needs to be set to ‘Act On Fault’ so the device will not ignore the faults. Enabling sequencing by resistor on the CFG pin sets both of these bits appropriately.
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How many devices can be use in a group?
The address group for fault spreading and event based sequencing is limited to 8 addresses. This was chosen to reduce internal firmware code size. A device receiving a Power Fail message from any other device in its group will shutdown immediately and wait for the proper sequencing order of a restart to occur. A device determines if a message is from another device in its group by masking the lower three address bits of the other device’s address (contained in the message) and comparing the result to its own address.
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Do Digital-DC devices need to be power cycled after the CPU sets a custom device configuration?
No, power cycling is not required. Almost all of the configuration commands can be issued real-time without requiring any power cycle, including the PID tap settings. Issuing a STORE_USER_ALL command after loading these new values will save the new settings in flash and the device will then load these settings every time it powers up thereafter.
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What is the monitor ADC sample rate?
The hardware measures current at a rate of Fsw/2 (the min and max current are read every half switching cycle) through the ADC, and the output of this ADC is used for fault management. The ADC output then goes into some filtering stages before storing the measured value, which can be read using the READ_IOUT command. The SMBus throughput is limited to 100us/byte, and it takes roughly 1ms to perform a read-back function using the PMBus command READ_IOUT. The current value measured by our device is updated every 3 ms to 5 ms, so issuing the command faster than every 3ms will result in the same value being reported.
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Can we provide a “max hold” function for current measurement?
Digital-DC devices do not have any threshold intended for this function, but an external CPU could monitor the current reading at regular intervals and provide the max current data over a specific time period. This is also something that we can easily incorporate into future devices as a standard function.
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How does our dead-time algorithm work?
Typical analog PWMs with this feature try to minimize the dead-time, but in doing so may get so low that they start to encounter cross-conduction due to variations in the capacitive nature of the MOSFETs used (this can vary from lot to lot). Our Digital-DC architecture instead is continuously trying to optimize the efficiency by looking for the minimum duty cycle based on a given input/output voltage ratio (this minimum duty cycle corresponds to the highest efficiency). The optimal efficiency point doesn’t always occur at the lowest dead-time setting. Additionally, our algorithm closes its loop around the power train components, so variations in the FET capacitance or other parameters are captured and compensated for in our calculation.
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What is the smallest MOSFET deadtime we can configure?
Digital-DC devices with external MOSFETs allow you to set the dead-times anywhere between approx -10ns (slight overlap) up to 60ns in 4ns steps. Our adaptive dead-time optimization routine has two safety settings that help prevent excessive cross-conduction:
There is a minimum duty cycle command that allows you to set a min duty cycle limit that is practical with respect to your application.
There is a hardware protection mechanism that prevents any more than an approx 10ns cross-conduction period at any time.
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Please also see general Zilker Labs FAQs.
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